1. Field of the Invention
The disclosure relates generally to methods for generating design layouts of integrated circuits (ICs), and more particularly to methods for automatically generating draft device layouts and allowing execution of scripts for modifying the draft device layouts, including re-generation of draft layouts based on modified parameter values.
2. Description of the Related Art
A typical IC includes a semiconductor substrate doped in a desired pattern and several layers of insulating and conductive materials sequentially formed above the substrate. The doping patterns in the substrate and the layer patterns define structures of IC devices such as gates, transistors and passive devices (inductors, capacitors and resistors), along with the conductive networks that interconnect the IC devices.
For custom layout designs, designers typically use parameterized cells (PCells) as building blocks. Traditionally, PCells are defined in scripting languages, of which some are proprietary, such as the Cadence SKILL language, and some are in the public domain, such as TCL or Python. To instantiate a script-based PCell in a layout, the designer needs to specify the PCell name and give a list of values for the parameters. The system then realizes the layout for the PCell instance by executing the corresponding script with the parameter values provided by the designer.
Although script-based PCells provide a flexible way for generating device layouts, the programming effort for the scripts is huge, and the subsequent maintenance of the scripts is difficult and complicated. Alternatively, a built-in device generator can be provided for reducing the effort needed for the scripts. U.S. Pat. No. 6,457,163 entitled “Method and system for constructing and manipulating a physical integrated circuit layout of a multiple-gate semiconductor devices” discloses an example of built-in device generator. For built-in device generators, a predefined set of elements can be programmed in the layout tool in advance, and the designer can select specific elements, wherein the corresponding layouts can be automatically generated by the built-in device generator. It is noted that the designer only needs to prepare and maintain design rules for the built-in device generator in layout tools. The built-in device generator is easy to use by the designer since no scripting or template designing is needed. Unfortunately, the predefined elements in the built-in device generator are limited to specific layout patterns. For new design rules/layout patterns which are not currently supported in a built-in device generator, the designer can do nothing but to wait since the device generator is provided by the tool vendor, and is purely a black box to the designer. This limitation can be alleviated if the built-in device generation is augmented with the power and flexibility of scripting as found in script-based PCells. U.S. Pat. No. 7,178,114 entitled “Scripted, hierarchical template-based IC physical layout system” discloses a method of embedding a script in a template-based IC layout generator. However, the script is tailored to the template-based generation approach. It does not offer a full-blown scripting capability such as querying and editing. Moreover, it lacks the capability of modifying parameter values and requesting for a re-generation.
What is needed is a device layout generation method that can automatically generate device layouts for ICs while allowing designers to provide scripts which can modify the device layouts including modifying parameter values and requesting for a re-generation, thus enabling the device generator to be easily extended or modified, and offer ease of use with great flexibility for layout design.